ECS HARDWARE and the GRAPHICS LIBRARY ------------------------------------- Typed for YOU by Conqueror of AGILE Thanks to Galactus! If you are interested in the information about the include files, structures in the graphics.library and how to program the ECS with Operating System friendly routines, contact me on one of our boards and I can mail or fax it to you. (I didn't bother to type it all in, at least not now, it was boring enough to type this! I am no [RYGAR]!) This was the most interesting part so thats why you got it! Contact me at: Pleasure Dome +46-16-127263 Graveyard +44-91-5160560 Illicit Illusion +1-717-399-3160 Datastorm +1-703-347-2078 Twilight Zone +49-511-456592 Or write to: Agile - BOX 12O44 - 63O 12 Eskilstuna - SWEDEN ---------------------------------------------------------------------------- The new Enhanced Chip Set consists of compatible revisions to the Agnus and Denise custom chips. V2.0 graphics.library software makes it possible for these chips to display images in new resolutions, at new monitor scan rates and with new sprite and genlock abilities. With these new features come certain new responsiblities for customers of the graphics.library. With the ECS Agnus, the V36 graphics.library supports the new programmable scan rate registers to provide multi-sync and bi-sync monitor capability. The new SuperHires mode provides 35ns pixel rates and sprite positioning at 70ns rates. Support for big blits (up to 32K x 32K) is provided for all graphics functions if the ECS Agnus is present. With the ECS Denise, the V36 graphics.library provides display window start and stop with explicit control over larger ranges than was possible before. There are new color register interpretations as part of the SuperHires mode. Genlock control has been expanded for more flexibility. Borders may be explicity transparent or opaque, color registers other than zero can control video overlay and a bitplane mask may be used for special-purpose video masking concurrently with the other genlock features. The register map listed below shows the changes and new registers in the Amiga's custom chips. A=Agnus chip, D=Denise chip, P=Paula chip, W=Write, R=Read, S=Strobe ---------------------------------------------------------------------------- ADD REGISTER V2.0 R/W CHIP FUNCTION ---------------------------------------------------------------------------- 004 VPOSR chg R A Read vertical most sig. bits (and frame flop) 012 POT0DAT chg R P Pot counter data left pair (vertical, horiz) 014 POT1DAT chg R P Pot counter daya right pair (vertical, horiz) 020 DSKPTH chg W A Disk pointer (high 5 bits, was 3 bits) 02E COPCON chg W A Coprocessor control 03E STRLONG chg S D Strobe for identification of long horiz line 042 BLTCON1 chg W A Blitter control register 1 050 BLTxPTH chg W A Blitter pointer to x (high 5 bits) 05A BLTCON0L new W A Blitter control 0, lower 8 bits (minterms) 05C BLTSIZV new W A Blitter V size (for 15 bit vertical start) 05E BLTSIZH new W A Blitter H size and start (for 11 bit H size) 078 SPRHDAT new W A Ext. logic UHRES sprite pointer and data id 07C DENISEID new R D Chip revision level for Denise (video out chip) 080 COP1LCH chg W A Coprocessor 1st location (high 5 bits) 084 CPO2LCH chg W A Coprocessor 2nd location (high 5 bits) 0A0 AUDxLCH chg W A Audio channel x location (high 5 bits) 0A6 AUDxPER chg W P Audio channel x period 100 BPLCON0 chg W A,D Bit plane control (miscellaneous control bits) 104 BPLCON2 chg W D Bit plane control (video priority control) 106 BPLCON3 new W D Bit plane control (enhanced features) 142 SPRxCTL chg W A Sprite x position and control data 1C0 HTOTAL new W A Highest number count, horiz line (VARBEAMEN=1) 1C2 HSSTOP new W A Horizontal line position for HSYNC stop 1C4 HBSTRT new W A Horizontal line position for HBLANK start 1C6 HBSTOP new W A Horizontal line position for HBLANK stop 1C8 VTOTAL new W A Highest numbered vertical line (VARBEAMEN=1) 1CA VSSTOP new W A Vertical line position for VSYNC stop 1CC VBSTRT new W A Vertical line position for VBLANK start 1CE VBSTOP new W A Vertical line position for VBLANK stop 1D0 SPRHSTRT new W A UHRES sprite vertical start 1D2 SPRHSTOP new W A UHRES sprite vertical stop 1D4 BPLHSTRT new W A UHRES bit plane vertical start 1D6 BPLHSTOP new W A UHRES bit plane vertical stop 1D8 HHPOSW new W A DUAL mode hires H beam counter write 1DA HHPOSR new R A DUAL mode hires H beam counter read 1DC BEAMCON0 new W A Beam counter control register (SHRES,UHRES,PAL) 1DE HSSTRT new W A Horizontal sync start (VARHSY) 1E0 VSSTRT new W A Vertical sync start (VARVSY) 1E2 HCENTER new W A Horizontal position for Vsync on interlace 1E4 DIWHIGH new W A,D Display window - upper bits for start, stop 1E6 BPLHMOD new W A UHRES bit plane modulo 1E8 SPRHPTH new W A UHRES sprite pointer (high 5 bits) 1EA SPRHPTL new W A UHRES sprite pointer (low 15 bits) 1EC BPLHPTH new W A Vram (UHRES) bit plane pointer (high 5 bits) 1EE BPLHPTL new W A Vram (UHRES) bit plane pointer (low 15 bits) Determining Chip Revisions -------------------------- The V36 graphics.library field GfxBase-ChipRevBits() contains bit defini- tions to tell you whether ECS is currently installed and activated. These bits are derived from registers new or changed on the ECS chips. The bit GFXF_HR_AGNUS indicates that HiRes Agnus from the ECS is installed. This is derived from the Agnus VPOSR register. The VPOSR register is defined as: VPOSR - Read vertical most significant bits (and frame flop) Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Use LOF I6 I5 I4 I3 I2 I1 I0 LOL - - - - V10 V9 V8 I0-I6 (bits 8-14) provide the chip identification. At present there are four possible settings. A value of 20 or 30 indicates HighRes Agnus from the ECS. 8361 (regular NTSC) or 8370 (fat NTSC) = 10 for NTSC Agnus 8367 (regular PAL) or 8371 (fat PAL) = 00 for PAL Agnus 8368 (hr) or 8372 (fat-hr) = 20 for PAL, 30 for NTSC Similarly, the graphics.library flag GFXF_HR_DENISE is derived from the Denise register DENISEID. This is a new register which can have of two values present. The original Denise (8362) does not have this register, so whatever value is left over on the bus from the last cycle will be there. The HighRes Denise (8373) from the ECS will return FC in the lower 8 bits. The upper 8 are reserved. SuperHires Mode --------------- SuperHires mode provides 35ns pixel display rate, twice as much horizontal resolution as Hires mode and four times the Lores rates. The nominal resolution of a SuperHires viewport is 1280 pixels. The maximum plane depth for a SuperHires viewport is 2 bitplanes which saturates DMS bandwidth as much as FOUR Hires bitplanes do. This mode is controlled by graphics.library writing to the BPLCON0 register in the LOF copperlist (/SHF if interlaced). BPLCON0 chg W A,D Bit plane control register (misc. control bits) Bit Use -------- 15 HIRES Set it to zero if SHRES enabled 14 BPU2 \ 13 BPU1 > Depth of SuperHires mode (1 or 2) 12 BPU0 / 11 HAM Incompatible with SuperHires mode 10 DPF Compatible with SuperHires mode 09 08 07 06 SHRES SuperHires 35ns pixel enable bit 05 BPLHWRM 04 SPRHWRM 03 LPEN Compatible with SuperHires mode 02 LACE Compatible with SuperHires mode 01 00 Programmers must NOT rely on interpreting ViewPort-Modes bits directly when determining the mode of a ViewPort. Beginning with V36 graphics.library, the ViewPort-Modes field is used for V1.2 compatibility ONLY. Under V1.2 the ViewPort-Modes field mirrored some of the BPLCON0 bits most notably Hires and Lace. However, other logical defines in this field such as the ViewPort-Modes PF2PRI bit conflict with the SHRES bit assignment in the actual hardware. For this reason, under V2.0 and above programmers will need to use the new DataBase/ModeID scheme to determine their ViewPort's mode, and to specify a mode when creating, cloning, or copying ViewPorts. For more on this refer to the section "Software and the Graphics.Library" below. SuperHires Mode and the Denise Color Registers ---------------------------------------------- SuperHires mode has a coarser granularity of color control than either Hires or Lores modes. This is because the timing of color conversions at these very high pixel rates requires special "tricks". There are only two bits of red, green and blue color resolution per hires pixel. In order to decode color information in the SuperHires mode for sprites and bitplanes, certain multiplexing occurs in the use of the registers. Instead of 4 bits of red, green and blue for for bitplane registers 0-3 stored as 0x0RGB in four color registers, SuperHires bitplane colors are encoded specially in the sixteen lower color registers: R G B Bitplane (Color 0) : ab- cd- ef- Bitplane (Color 1) : gh- ij- kl- Bitplane (Color 2) : mn- op- qr- Bitplane (Color 3) : st- uv- wx- Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 C 00 . . . . a b a b c d c d e f e f O 01 . . . . g h a b i j c d k l e f L 02 . . . . m n a b o p c d q r e f O 03 . . . . s t a b u v c d w x e f R 04 . . . . a b g h c d i j e f k l 05 . . . . g h g h i j i j k l k l R 06 . . . . m n g h o p i j q r k l E 07 . . . . s t g h u v i j w x k l G 08 . . . . a b m n c d o p e f q r I 09 . . . . g h m n i j o p k l q r S 0A . . . . m n m n o p o p q r q r T 0B . . . . s t m n u v o p w x q r E 0C . . . . a b s t c d u v e f w x R 0D . . . . g h s t i j u v k l w x 0E . . . . m n s t o p u v q r w x 0F . . . . s t s t u v u v w x w x SuperHires sprites are encoded in the upper sixteen color registers using a similar scheme: R G B Sprite (Color 0) : AB- CD- EF- Sprite (Color 1) : GH- IJ- KL- Sprite (Color 2) : MN- OP- QR- Sprite (Color 3) : ST- UV- WX- Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 C 10 . . . . A B A B C D C D E F E F O 11 . . . . G H A B I J C D K L E F L 12 . . . . M N A B O P C D Q R E F O 13 . . . . S T A B U V C D W X E F R 14 . . . . A B G H C D I j E F K L 15 . . . . G H G H I J I J K L K L R 16 . . . . M N G H O P I J Q R K L E 17 . . . . S T G H U V I J W X K L G 18 . . . . A B M N C D O P E F Q R I 19 . . . . G H M N I J O P K L Q R S 1A . . . . M N M N O P O P Q R Q R T 1B . . . . S T M N U V O P W X Q R E 1C . . . . A B S T C D U V E F W X R 1D . . . . G H S T I J U V K L W X 1E . . . . M N S T O P U V R R W X 1F . . . . S T S T U V U V Q X W X SuperHires color encryption is not reflected in the ColorTable. The color encoding is, however, reflected in the ViewPort's copper lists by graphics via MakeVPort(), SetRGB4(), etc. Keep in mind that because of the loss of lower bits of precision in speci- fying SuperHires colors, pastel colors in a closely graduated color scheme may be visually difficult to distinguish from each other. SuperHires 70ns Sprite Positioning ---------------------------------- SuperHires mode has a finer granularity of sprite positioning than either Hires or Lores modes. This allows for positioning the sprite every other SuperHires pixel on 70ns boundaries. The ECS registers SPRxPOS and SPRxCTL work together as position, size and sprite feature control registers. They are usually loaded by the sprite DMA channel, during the horizontal blank, however they may be loaded by the processor. The two registers are defined as follows: SPRxPOS W A,D Sprite x vertical-horizontal start position data Bit Use ---------- 15-08 07-00 SH8-SH1 Start horizontal value. Low bit (SH0) in SPRxCTL. SPRxCLT W A,D Sprite x position and control data Bit Use ---------- 15-08 07 06 05 04 SHSH1 Start horizontal (SHR mode) 70ns increment 03 SHSH0 Start horizontal (SHR mode) 35ns (unimplemented) 02 01 00 SH0 Start horiz. value. Low bit 140ns increment Note: Bits 3 and 4 are in the ECS chips only. 70ns sprite positions are only available in SuperHires mode. Multi-Sync and Bi-Sync Monitors ------------------------------- The ECS Agnus now includes registers for setting a standard programmable scan rate. The scan rate supported in the V36 graphics.library include: NTSC (525 lines, 227.5 colorclocks per scan line) PAL (625 lines, 227.5 colorclocks per scan line) VGA (525 lines, 114.0 colorclocks per scan line) The V36 graphics.library controls the variable number of colorclocks on each horizontal scan line with a combination of registers. Each combination of registers provides a different frequency of scan rate and number of lines per display field: HTOTAL W A Highest number count in horizontal line Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Use 0 0 0 0 0 0 0 0 H8 H7 H6 H5 H4 H3 H2 H1 The horizontal line has this many + 1280ns increments. VTOTAL W A Highest numbered vertical line This is the line number as which to reset the vertical position counter. There are this many + 1 lines in a field. The exception is if the INTERLACE bit is set (BPLCON0), in which case the long field is this many + 2 and the short field this many + 1. Programmable syncronization is implemented through five new ECS Agnus registers: VSSTRT W A Vertical line position for VSYNC start VSSTOP W A Vertical line position for VSYNC stop HSSTRT W A Horizontal line position for HSYNC start HSSTOP W A Horizontal line position for HSYNC stop HCENTER W A Horizontal position for VSYNC on interlace A reasonable composite can be generated by setting HCENTER half a horizontal line from HSSTRT, and HBSTOP at (HSSTOP-HSSTRT) before HCENTER, with HBSTRT at (HSSTOP-HSSTRT) before HSSTRT. Programmable blanking is implemented through four new ECS Agnus registers: HBSTRT W A Horizontal line position for HBLANK start HBSTOP W A Horizontal line position for HBLANK stop VBSTRT W A Vertical line position for VBLANK start VBSTOP W A Vertical line position for VBLANK stop A new register in ECS Agnus, BEAMCON0, provides a programmable signal generator: BEAMCON0 W A Beam counter control register Bit Use ---------- 15 14 HARDDIS Disable hardwired vertical/horizontal blank 13 LPENDIS Ignore lathced pen value on vertical pos read 12 VARVBEN Use VBSTRT/STOP disable hard window stop 11 LOLDIS Disable long line/short line toggle 10 CSCBEN Composite sync redirection 09 VARVSYEN Variable vertical sync enable 08 VARHSYEN Variable horizontal sync enable 07 VARBEAMEN Variable beam counter comparator enable 06 DUAL Special ultra resoultion mode enable 05 PAL Programmable PAL mode enable 04 VARCSYEN Variable composite sync 03 BLANKEN Composite blank redirection 02 CSYTRUE Polarity control for C sync pin 01 VSYTRUE Polarity control for V sync pic 00 HSYTRUE Polarity control for H sync pin Programmable changes between PAL and NTSC modes are new for V2.0. They rely on hardware sync and blank in the Agnus/Denise chipset to guarantee necessary signals for a correctly displayed picture. Other modes, such as VGA (31 kHz programmable mode) disable the hard stops on display sync and blank. Do not write to this register. Incorrect software writing directly to BEAMCON0 has the (remote) chance of destroying your extremely expensive multisync monitor. The new graphics.library and the ECS provide a more powerful display window specification. The registers DIWSTRT and DIWSTOP control the display window size and position: DIWSTRT W A,D Display window start (upper left vert-hor pos) DIWSTOP W A,D Display window stop (lower right vert-hor pos) Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Use V7 V6 V5 V4 V3 V2 V1 V0 H7 H6 H5 H4 H3 H2 H1 H0 The way these two registers work have been changed. DIWSTRT used to be vertically restricted to the upper 2/3 of the display (V8=0), and horizon- tally restricted to the left 3/4 of the display (H8=0). DIWSTOP used to be vertically restricted to the lower 1/2 of the display and horizontally to the right 1/4 of the display (H8=1). The V36 graphics.library now supports explicit display window start and stop positions within a larger and more useful range of values, via control of the new DIWHIGH register in the ViewPort copper lists: DIWHIGH W A,D Display window upper bits for start, stop Bit Use ---------- 15 0 14 0 13 H8 Horizontal stop, most significant bit. 12 0 11 0 10 V10 \ 09 V9 > Vertical stop, most significant 3 bits. 08 V8 / 07 0 06 - 05 H8 Horizontal start, most significant bit. 04 0 03 0 02 V10 \ 01 V9 > Vertical stop, most significant 3 bits. 00 V8 / This is an added register for the ECS chips, and allows larger start and stop ranges. If it is not written, the old scheme for DIWSTRT and DIWSTOP described above holds. If this register is written last in a sequence of setting the display window, it sets direct start and stop positions anywhere on the screen. When the ECS Denise chip is available, graphics.library will set upp copper lists using the new, explicit display window controls. Programs which conistently call MakePort(), MrgCop(), and Loadview() when changing the vertical position of their ViewPort (DxOffset) will continue to behave normally. Programs which failed to call MakeVPort() when moving the ViewPort verti- cally may no longer be displayed correctly. Genlock Extensions ------------------ The V36 graphics.library supports the new genlock capabilities of the ECS Denise chip in PAL or NTSC modes. Any color register may be chosen as controlling video overlay (COLORKEY). A single bitplane may be chosen to control video overlay as well (BITPLANEKEY). The border areas surrounding the active picture may also be set to opaque or transparent. BPLCON0 W A,D Bit plane control (miscellaneous control bits) BPLCON1 W D Bit plane control (horizontal scroll control) BPLCON2 W D Bit plane control (video priority control) BPLCON3 W D Bit plane control (enhanced features) Bit BPLCON0 BPLCON1 BPLCON2 BPLCON3 ----------------------------------------- 15 14 ZDBPSEL2 \ 13 ZDBPSEL1 > Select bitplane 12 ZDBPSEL0 / 11 ZDBPEN Use BITPLANEKEY 10 ZDCTEN Use COLORKEY 09 KILLEHB Kill halfbrite 08 07 06 05 BRDRBLNK Border blank 04 BRDRTRAN Border opaque 03 02 01 00 ENBPLCN3 Enable the new BPLCON3 register. The ECS genlock features are enabled on via a ViewPort by ViewPort basis. Genlock has been designed to workwith NTSC and PAL modes only. Genlock and 31 kHz programmable scan rates are not compatible modes. Big Blits --------- The V36 graphics.library supports the ECS Agnus Blitter enhancements, which provide for contiguous blits of up to 32768 x 32768 pixels at a time. Under the original chip set 1024 x 1024 was the maximum: BLTSIZE W A Old Blitter size and start (window width, height) Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Use H9 H8 H7 H6 H5 H4 H3 H2 H1 H0 W5 W4 W3 W2 W1 W0 H = Height (10 bit height = 1024 lines max) W = Widht (6 bit width = 1024 pixels max) Two new registers have been added which make larger blits possible: BLTSIZV W A ECS Blitter vertical size Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Use 0 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 H0 H = Height (15 bit height = 32768 lines max) BLTSIZH W A ECS Blitter horizontal size and start Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Use 0 0 0 0 0 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 W0 W = Width (11 bit width = 32768 pixels max) With these two registers, blits up to 32K by 32K are now possible - much larger than the original chipset could accept. The original commands are retained for compability. BLTSIZV should always be written first, followed by BLTSIZH, which starts the blitter. The existence of the ECS Agnus Blitter is reflected in the state of the GfxBase-ChipRevBits bit definition GFXB_BIG_BLITS and is initialized by the graphics.library at powerup. Note that the hardware/blits.h constant MAXBYTESPERROW has been redefined to reflect the larger range of legal blitter operations. If the ECS Blitter is accessable, the graphics.library supports its use for all graphics functions including areafill, gels, line and ellipse drawing functions. If the ECS Blitter is NOT installed, programmers should limit the absolute size of their RastPorts to values that the old BLTSIZE register can address. Typed for YOU by Conqueror of AGILE